1. Field of the Invention
The present invention relates to integrated circuit technology. More particularly, the present invention relates to circuits and methods for testing on-chip power-on-reset circuits
2. The Prior Art
In an integrated circuit, a power-on-reset circuit is used to generate a negative or positive pulse to reset the entire chip when power is ramping up so that the on-chip circuitry is in a known reset state. The highest VCC at which the whole chip is still in the reset mode is called the power-on-reset trip point.
The power-on-reset trip point can not be set to too low a value because the on-chip circuitry will not be working properly at values of VCC that are too low. In other words, the entire chip will not be reset properly to a known reset state. In addition, the power-on-reset trip point can not be set to too high a value because the on-chip circuitry will still be in reset mode at too high a value of VCC.
In order to determine the power-on-reset trip point, the minimum value of VCC at which the chip is still working is characterized during the debugging and qualification stages of the chip development. Due to process variations, including, but not limited to lot-to-lot variations, wafer-to-wafer variations, variations across a wafer, or individual defects, or the sensitivities of the power-on-reset circuit to temperature, layout, or process parameters, the actual power-on-reset trip point may vary from die to die and may be different from the characterized value.
The power-on-reset trip point is not tested, or not 100% tested before shipping. In the prior art, no special power-on-reset trip point test circuit is embedded. The power-on-reset trip point shift, especially shifting to a lower trip point, is causing field application failure.